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HD-6409
March 1997
CMOS Manchester Encoder-Decoder
Description
The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned silicon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deficiencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This minimizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Manchester code is used in magnetic tape recording and in fiber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers.
Features
* Converter or Repeater Mode * Independent Manchester Encoder and Decoder Operation * Static to One Megabit/sec Data Rate Guaranteed * Low Bit Error Rate * Digital PLL Clock Recovery * On Chip Oscillator * Low Operating Power: 50mW Typical at +5V * Available in 20 Lead Dual-In-Line and 20 Pad LCC Package
Ordering Information
PACKAGE PDIP SOIC CERDIP DESC CLCC DESC TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to 125oC -40oC to +85oC -55oC to 125oC 1 MEGABIT/SEC HD3-6409-9 HD9P6409-9 HD1-6409-9 5962-9088801MRA HD4-6409-9 5962-9088801M2A PKG. NO. E20.3 M20.3 F20.3 F20.3 J20.A J20.A
Pinouts
HD-6409 (CERDIP, PDIP, SOIC) TOP VIEW HD-6409 (CLCC) TOP VIEW
BOO 19 18 BZO 17 SS 16 ECLK 15 CTS 14 MS 9 RST 10 GND 11 CO 12 IX 13 OX
BZI BOI UDI SD/CDS SDO SRST NVM DCLK RST
1 2 3 4 5 6 7 8 9
20 VCC 19 BOO 18 BZO 17 SS 16 ECLK 15 CTS 14 MS 13 OX 12 IX 11 CO NVM DCLK 7 8 SD/CDS SDO SRST 4 5 6
3
2
1
20
GND 10
VCC
BOI
UDI
BZI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2951.1
5-1
HD-6409 Block Diagram
SDO NVM BOI BZI UDI EDGE DETECTOR RST SD/CDS RESET SD INPUT/ OUTPUT SELECT MANCHESTER ENCODER COMMAND SYNC GENERATOR CTS DATA INPUT LOGIC 5-BIT SHIFT REGISTER AND DECODER OUTPUT SELECT LOGIC BOO BZO
SRST
MS IX OX CO SS OSCILLATOR ECLK DCLK
COUNTER CIRCUITS
Logic Symbol
SS CO
17 11
13 CLOCK GENERATOR 12
OX IX
SD/CDS ECLK
4 16 ENCODER
19 18 15
BOO BZO CTS
MS RST SDO DCLK NVM SRST
14 9 5 8 7 6
CONTROL 2 1 3 BOI BZI UDI
DECODER
5-2
HD-6409 Pin Description
PIN NUMBER 1 TYPE I SYMBOL BZl NAME Bipolar Zero Input DESCRIPTION Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for data input, UDI must be held low. In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received. Ground Buffered output of clock input IX. May be used as clock signal for other peripherals. IX is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. If the internal oscillator is used, OX and IX are used for the connection of the crystal. MS must be held low for operation in the converter mode, and high for operation in the repeater mode. In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop.
2
I
BOl
Bipolar One Input
3
I
UDI
Unipolar Data Input
4
I/O
SD/CDS
Serial Data/Command Data Sync
5 6
O O
SDO SRST
Serial Data Out Serial Reset
7
O
NVM
Nonvalid Manchester
8 9
O I
DCLK RST
Decoder Clock Reset
10 11 12 13 14 15
I O I O I I
GND CO IX OX MS CTS
Ground Clock Output Clock Input Clock Drive Mode Select Clear to Send
16
O
ECLK
Encoder Clock
5-3
HD-6409 Pin Description
PIN NUMBER 17 18 19 20 NOTE: (I) Input TYPE I O O I SYMBOL SS BZO BOO VCC (O) Output NAME Speed Select Bipolar Zero Output Bipolar One Out VCC DESCRIPTION A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency. BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state. See pin 18. VCC is the +5V power supply pin. A 0.1F decoupling capacitor from VCC (pin20) to GND (pin-10) is recommended.
Encoder Operation
The encoder uses free running clocks at 1X and 2X the data rate derived from the system clock lX for internal timing. CTS is used to control the encoder outputs, ECLK, BOO and BZO. A free running 1X ECLK is transmitted out of the encoder to drive the external circuits which supply the NRZ data to the MED at pin SD/CDS. A low on CTS enables encoder outputs ECLK, BOO and BZO, while a high on CTS forces BZO, BOO high and holds ECLK low. When CTS goes from high to low 1 , a synchronization sequence is transmitted out on BOO and BZO. A synchronization sequence consists of eight Manchester "0"
CTS 1 ECLK
bits followed by a command sync pulse. 2 A command sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high followed by 1 1/2 bits low. 3 Serial NRZ data is clocked into the encoder at SD/CDS on the high to low transition of ECLK during the command sync pulse. The NRZ data received is encoded into Manchester II data and transmitted out on BOO and BZO following the command sync pulse. 4 Following the synchronization sequence, input data is encoded and transmitted out continuously without parity check or word framing. The length of the data block encoded is defined by CTS. Manchester data out is inverted.
SD/CDS `1' BZO `1' BOO `0' `1' 20 0 0 `0' `1'
DON'T CARE
0
0
0
0
03
4
EIGHT "0's"
COMMAND SYNC
SYNCHRONIZATION SEQUENCE tCE6 tCE5
FIGURE 1. ENCODER OPERATION
Decoder Operation
The decoder requires a single clock with a frequency 16X or 32X the desired data rate. The rate is selected on the speed select with SS low producing a 16X clock and high a 32X clock. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The internal operation of the decoder utilizes a free running clock synchronized with incoming data for its clocking. The Manchester II encoded data can be presented to the decoder in either of two ways. The Bipolar One and Bipolar Zero inputs will accept data from differential inputs such as a comparator sensed transformer coupled bus. The Unipolar Data input can only accept noninverted Manchester II encoded data i.e. Bipolar One Out through an inverter to Unipolar Data Input. The decoder continuously monitors this data input for valid sync pattern. Note that while the MED encoder section can generate only a command sync pattern, the decoder can recognize either a command or data sync pattern. A data sync is a logically inverted command sync.
5-4
HD-6409
There is a three bit delay between UDI, BOl, or BZI input and the decoded NRZ data transmitted out of SDO. Control of the decoder outputs is provided by the RST pin. When RST is low, SDO, DCLK and NVM are forced low. When RST is high, SDO is transmitted out synchronously with the recovered clock DCLK. The NVM output remains low after a low to high transition on RST until a valid sync pattern is received.
DCLK
The decoded data at SDO is in NRZ format. DCLK is provided so that the decoded bits can be shifted into an external register on every high to low transition of this clock. Three bit periods after an invalid Manchester bit is received on UDI, or BOl, NVM goes low synchronously with the questionable data output on SDO. FURTHER, THE DECODER DOES NOT REESTABLISH PROPER DATA DECODING UNTIL ANOTHER SYNC PATTERN IS RECOGNIZED.
UDI COMMAND SYNC SDO 1 0 0 1 0 1 0 1 0 1 0 1 0
RST
NVM
FIGURE 2. DECODER OPERATION
Repeater Operation
Manchester Il data can be presented to the repeater in either of two ways. The inputs Bipolar One In and Bipolar Zero In will accept data from differential inputs such as a comparator or sensed transformer coupled bus. The input Unipolar Data In accepts only noninverted Manchester II coded data. The decoder requires a single clock with a frequency 16X or 32X the desired data rate. This clock is selected to 16X with Speed Select low and 32X with Speed Select high. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The inputs UDl, or BOl, BZl are delayed approximately 1/2 bit period and repeated as outputs BOO and BZO. The 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO.
INPUT COUNT ECLK SYNC PULSE UDI 1 2 3
A low on CTS enables ECLK, BOO, and BZO. In contrast to the converter mode, a transition on CTS does not initiate a synchronization sequence of eight 0's and a command sync. The repeater mode does recognize a command or data sync pulse. SD/CDS is an output which reflects the state of the most recent sync pulse received, with high indicating a command sync and low indicating a data sync. When RST is low, the outputs SDO, DCLK, and NVM are low, and SRST is set low. SRST remains low after RST goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. The reset bit is the first data bit after the sync pulse. With RST high, NRZ Data is transmitted out of Serial Data Out synchronously with the 1X DCLK.
4 5 6 7
BZO
BOO
RST
SRST
FIGURE 3. REPEATER OPERATION
5-5
HD-6409 Manchester Code
Nonreturn-to-Zero (NRZ) code represents the binary values logic-O and Iogic-1 with a static level maintained throughout the data cell. In contrast, Manchester code represents data with a level transition in the middle of the data cell. Manchester has bandwidth, error detection, and synchronization advantages over NRZ code. The Manchester II code Bipolar One and Bipolar Zero shown below are logical complements. The direction of the transition indicates the binary value of data. A logic-0 in Bipolar One is defined as a Low to high transition in the middle of the data cell, and a logic-1 as a high to low mid bit transition, Manchester Il is also known as Biphase-L code. The bandwidth of NRZ is from DC to the clock frequency fc/2, while that of Manchester is from fc/2 to fc. Thus, Manchester can be AC or transformer coupled, which has considerable advantages over DC coupling. Also, the ratio of maximum to minimum frequency of Manchester extends one octave, while the ratio for NRZ is the range of 5-10 octaves. It is much easier to design a narrow band than a wideband amp. Secondly, the mid bit transition in each data cell provides the code with an effective error detection scheme. If noise produces a logic inversion in the data cell such that there is no transition, an error indiction is given, and synchronization must be re-established. This places relatively stringent requirements on the incoming data.
BIT PERIOD BINARY CODE NONRETURN TO ZERO 1 0
The synchronization advantages of using the HD-6409 and Manchester code are several fold. One is that Manchester is a self clocking code. The clock in serial data communication defines the position of each data cell. Non self clocking codes, as NRZ, often require an extra clock wire or clock track (in magnetic recording). Further, there can be a phase variation between the clock and data track. Crosstalk between the two may be a problem. In Manchester, the serial data stream contains both the clock and the data, with the position of the mid bit transition representing the clock, and the direction of the transition representing data. There is no phase variation between the clock and the data. A second synchronization advantage is a result of the number of transitions in the data. The decoder resynchronizes on each transition, or at least once every data cell. In contrast, receivers using NRZ, which does not necessarily have transitions, must resynchronize on frame bit transitions, which occur far less often, usually on a character basis. This more frequent resynchronization eliminates the cumulative effect of errors over successive data cells. A final synchronization advantage concerns the HD-6409's sync pulse used to initiate synchronization. This three bit wide pattern is sufficiently distinct from Manchester data that a false start by the receiver is unlikely.
2 1
3 1
4 0
5 0
BIPOLAR ONE BIPOLAR ZERO
FIGURE 4. MANCHESTER CODE
Crystal Oscillator Mode
C1 IX 16MHz X1 C1 = 32pF C0 = CRYSTAL + STRAY X1 = AT CUT PARALLEL RESONANCE FUNDAMENTAL MODE RS (TYP) = 30 OX R1 = 15M CO
LC Oscillator Mode
C1 IX C1 = 20pF C0 = 5pF L C1 - 2C0 C E ------------------------2 1 f O ---------------------2 LC e
C0
R1
C1 C1
OX
FIGURE 5. CRYSTAL OSCILLATOR MODE
FIGURE 6. LC OSCILLATOR MODE
5-6
HD-6409 Using the 6409 as a Manchester Encoded UART
BIPOLAR IN BIPOLAR IN
BZI BOI UDI SD/CDS SDO SRST NVM DCLK
VCC BOO BZO SS ECLK CTS MS OX IX CO CTS BIPOLAR OUT BIPOLAR OUT
RESET
RST GND
LOAD A B CK `164 QH A B CK `164 CK LOAD `165 QH SI CK LOAD QH `165
CP
DATA IN `273
DATA IN `273
PARALLEL DATA IN
PARALLEL DATA OUT
FIGURE 7. MANCHESTER ENCODER UART
5-7
HD-6409
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 83oC/W 23oC/W CLCC Package . . . . . . . . . . . . . . . . . . . . 95oC/W 26oC/W PDIP Package . . . . . . . . . . . . . . . . . . . . . 75oC/W N/A SOIC Package . . . . . . . . . . . . . . . . . . . . . 100oC/W N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC ( Lead Tips Only for Surface Mount Packages)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . .50ns Max NOTES: 1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by 2 IX clock cycles (16X mode) or 6 IX clock cycles (32X mode). 3. The maximum zero crossing tolerance is 2 IX clock cycles (16X mode) or 6 IX clock cycles (32 mode) from the nominal. Sync. Transition Span (t2) . . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2) Short Data Transition Span (t4). . . . . . .0.5DBP Typical, (Notes 1, 2) Long Data Transition Span (t5) . . . . . . .1.0DBP Typical, (Notes 1, 2) Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . .(Note 3)
DC Electrical Specifications
SYMBOL VIH VIL VIHR VILR VIHC VILC II II IO VOH VOL ICCSB ICCOP FT NOTES:
VCC = 5.0V 10%, TA = -40oC to +85o (HD-6409-9) MIN 70% VCC VCC -0.5 VCC -0.5 -1.0 -20 -10 VCC -0.4 MAX 20% VCC GND +0.5 GND +0.5 +1.0 +20 +10 0.4 100 18.0 UNITS V V V V V V A A A V V A mA (NOTE 1) TEST CONDITIONS VCC = 4.5V VCC = 4.5V VCC = 5.5V VCC = 4.5V VCC = 5.5V VCC = 4.5V VIN = VCC or GND, VCC = 5.5V VIN = VCC or GND, VCC = 5.5V VOUT = VCC or GND, VCC = 5.5V IOH = -2.0mA, VCC = 4.5V (Note 2) IOL = +2.0mA, VCC = 4.5V (Note 2) VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 16.0MHz, VIN = VCC or GND VCC = 5.5V, CL = 50pF (Note 1)
PARAMETER Logical "1" Input Voltage Logical "0" Input Voltage Logic "1" Input Voltage (Reset) Logic "0" Input Voltage (Reset) Logical "1" Input Voltage (Clock) Logical "0" Input Voltage (Clock) Input Leakage Current (Except IX) Input Leakage Current (IX) I/O Leakage Current Output HIGH Voltage (All Except OX) Output LOW Voltage (All Except OX) Standby Power Supply Current Operating Power Supply Current Functional Test
1. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH VCC/2, and VOL VCC/2, VCC = 4.5V and 5.5V. 2. Interchanging of force and sense conditions is permitted TA = +25oC, Frequency = 1MHz PARAMETER Input Capacitance Output Capacitance TYP 10 12 UNITS pF pF TEST CONDITIONS All measurements are referenced to device GND
Capacitance
SYMBOL CIN COUT
5-8
HD-6409
AC Electrical Specifications
SYMBOL fC tC t1 t3 tCH tCL tCE1 tCE2 tCD2 tR2 tr tf tr tf tCE3 tCE4 tCE5 tCE6 tCE7 tCD1 tCD3 tCD4 tR1 tR3 NOTES: 1. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH VCC/2, VOL VCC/2, VCC = 4.5V and 5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF. 2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested. 3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. VCC = 5.0V 10%, TA = -40oC to +85oC (HD-6409-9) MIN 1/fC tC+10 20 20 120 0 0.5 0.5 10.5 1.5 2.5 0.5 0.5 0.5 2.5 MAX 16 tC-10 40 40 50 50 11 11 1.0 1.5 11.5 1.0 2.5 3.0 1.5 1.5 1.0 3.0 UNITS MHz sec ns ns ns ns ns ns ns ns ns ns ns ns DBP DBP DBP DBP DBP DBP DBP DBP DBP DBP f = 16.0MHz f = 16.0MHz From 1.0V to 3.5V, CL = 50pF, Note 2 From 3.5V to 1.0V, CL = 50pF, Note 2 From 1.0V to 3.5V, CL = 20pF, Note 2 From 3.5V to 1.0V, CL = 20pF, Note 2 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 Notes 2, 3 (NOTE 1) TEST CONDITIONS -
PARAMETER Clock Frequency Clock Period Bipolar Pulse Width One-Zero Overlap Clock High Time Clock Low Time Serial Data Setup Time Serial Data Hold Time DCLK to SDO, NVM ECLK to BZO Output Rise Time (All except Clock) Output Fall Time (All except Clock) Clock Output Rise Time Clock Output Fall Time ECLK to BZO, BOO CTS Low to BZO, BOO Enabled CTS Low to ECLK Enabled CTS High to ECLK Disabled CTS High to BZO, BOO Disabled UDI to SDO, NVM RST Low to CDLK, SDO, NVM Low RST High to DCLK, Enabled UDI to BZO, BOO UDI to SDO, NVM
5-9
HD-6409 Timing Waveforms
NOTE: UDI = 0, FOR NEXT DIAGRAMS BIT PERIOD BOI
T1
BIT PERIOD
BIT PERIOD
T2 BZI COMMAND SYNC
T1
T3
T3
T2
BOI T2
T1
T1
T3
T3
BZI DATA SYNC T2
BOI BZI
T1 T3 T3
T1 T3 T1 T4 T3 T3
T5 ONE ZERO
T5 ONE
T4
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS
UDI
T2 COMMAND SYNC
T2
UDI
T2 DATA SYNC
T2
UDI
T4 ONE
T5 ZERO
T5 ONE
T4
T4 ONE
FIGURE 8.
tC tr 10% 90% tCH tf tCL
tr 3.5V 1.0V
tf
FIGURE 9. CLOCK TIMING
FIGURE 10. OUTPUT WAVEFORM
5-10
HD-6409 Timing Waveforms
(Continued)
ECLK tCE2 tCE1 SD/CDS tCE3 BZO BOO
FIGURE 11. ENCODER TIMING
CTS CTS BZO BOO tCE4 BZO tCE5 ECLK BOO ECLK tCE7 tCE6
FIGURE 12. ENCODER TIMING
FIGURE 13. ENCODER TIMING
DCLK tCD5
UDI MANCHESTER MANCHESTER MANCHESTER MANCHESTER LOGIC-1 LOGIC-0 LOGIC-0 LOGIC-1 tCD1 tCD2 SDO
tCD2 NVM
NRZ LOGIC-1
NOTE: Manchester Data-In is not synchronous with Decoder Clock. Decoder Clock is synchronous with decoded NRZ out of SDO. FIGURE 14. DECODER TIMING
RST
50% tCD3
RST
50% tCD4
DCLK, SDO, NVM
50%
DCLK
FIGURE 15. DECODER TIMING
FIGURE 16. DECODER TIMING
5-11
HD-6409 Timing Waveforms
UDI MANCHESTER `1' ECLK tR2 tR1 BZO MANCHESTER `1' tR3 SDO tR3 NVM MANCHESTER `0' MANCHESTER `0' tR2 MANCHESTER `0' MANCHESTER `0' MANCHESTER `1'
(Continued)
FIGURE 17. REPEATER TIMING
Test Load Circuit
DUT CL (NOTE)
NOTE: INCLUDES STRAY AND JIG CAPACITANCE
FIGURE 18. TEST LOAD CIRCUIT
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Sales Office Headquarters
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